FIG. 1 shows a known semiconductor device such as an NFET or PFET isolated by shallow trench isolation regions (STI) to form a structure 100. The structure 100 includes a semiconductor (e.g., silicon) substrate or wafer 102, a source region 104, a drain region, 106, a gate 108, an oxide layer 110, a body region 111, and a channel region 12 between the source region 104 and the drain region 106. As is well-known in the art, a voltage differential between the source region 104 and the drain region 106 induces an electric field across the channel region 112. A gate potential applied to the gate 108 can create an inversion layer in the body region 111 allowing the channel region 112 to form between the source region 104 and the drain region 106. This electric field is expressed in terms of the voltage differential between the source region 104 and the drain region 106 per the length of the channel region 112.
The structure 100 typically also includes isolation regions STI in order to isolate electrically each semiconductor device from other semiconductor devices. A plurality of isolation regions STI are formed in the semiconductor substrate 102 in order to isolate electrically a plurality of semiconductor devices formed in the semiconductor substrate. The isolation regions illustrated in FIG. 1 are shallow trench isolation (STI) regions formed by anisotropically etching the semiconductor substrate 102 to form trenches. A thermal oxide liner layer is grown by conventional methods to a thickness of about 10 Å to about 100 Å, such as by exposing the semiconductor substrate 102 to an oxygen ambient at a temperature about 185° C. to about 1150° C. The trenches are subsequently filled with an insulating material such as silicon oxide, by a conventional CVD process to form the isolation regions STI. Some of the conventional methods of filling a trench with silicon oxide include a) tetraethylorthosilicate low pressure chemical vapor deposition (LPTEOS), b) non-surface sensitive TEOS-ozone atmospheric pressure or sub-atmospheric chemical vapor deposition (APCVD or SACVD), and c) silane oxidation high-density plasma CVD, all as well known to those skilled in the art.
It is also known that compressive stress or tensile stress materials disposed in the structure can enhance charge carrier mobility. In order to maximize the performance of both NFETs and PFETs within an integrated circuit (IC) chip which includes numerous structures 100, tensile nitride liners have been used on NFETs and compressive nitride liners have been used on PFETs. The liners applied desired stresses to the channel. See for example, Yang et al, IEDM 2004, p 978, incorporated herein, and commonly-owned U.S. patent applications: Ser. No. 10/905,025 filed Dec. 10, 2004, Ser. No. 10/905,027 filed Dec. 10, 2004, Ser. No. 10/905,024 filed Dec. 10, 2004, which are all incorporated herein in their entireties.
It is also known that piezoresistance coefficients for doped Si in the crystal orientation X=[100], Y=[010], Z=[001], are as follows (Smith, Phys. Rev. V94, 1954, beginning on p. 42):
×10−11Pa−1.n-Sip-SiΠ11−102+6.6Π12+53.4−1.1Π44−13.6138.1
It has been shown that for PFETs in rotated wafers (with orientations X=[100], Y=[010], Z=[001]), the longitudinal and transverse stress effects are small (Okagaki, et al., VLSI, 2004, pgs. 120-121). This is because the constants Π11 and Π12 are small. The Smith and Okagaki references are incorporated herein in their entireties.